1. Field of the Invention
The present invention relates to a semiconductor device and method of manufacturing this semiconductor device. This device has an improved factor of effective mounting area, which represents the ratio of chip area of the semiconductor device to occupation area of the semiconductor device as actually mounted on a mounting substrate, such as a printed circuit board.
2. Description of the Related Art
A common semiconductor in which an element, such as a bipolar IC or a MOSLSI, is formed on a silicon substrate may have a constitution as shown in FIG. 1, where numeral 1 represents a silicon substrate, numeral 2 represents an island such as a cooling wheel on which the silicon substrate 1 is mounted, numeral 3 represents lead terminals, and numeral 4 represents a sealing resin mold.
As described above, the silicon substrate 1 on which a bipolar IC is formed is firmly mounted on the island 2, such as, a cooling wheel mainly including a copper by a soldering material 5, such as solder as shown in FIG. 1. The lead terminals 3 arranged on the peripheries of the silicon substrate 1 and each electrode of the bipolar IC or the like are electrically connected by wire bonding. The silicon substrate and portions of the lead terminals are completely coated with thermohardening resin 4, such as epoxy resin, by transfer molding. A resin molding type semiconductor device is thereby provided.
A semiconductor device molded with resin is normally mounted on a wiring substrate, such as a glass epoxy substrate. The semiconductor device is then electrically connected with other semiconductor devices and circuit elements mounted on a mounting substrate, and is used as a component for performing a prescribed circuit operation.
A mounting area of a mounting substrate 30 on which a semiconductor device 20 is mounted is represented by a region enclosed by lead terminals 21, 22, and 23 and a conductive pad to be connected with these lead terminals, as shown in FIG. 2. The mounting area is larger than the area of the silicon substrate (semiconductor chip) in the semiconductor device 20, but the majority of the mounting area is occupied by mold resin and lead terminals. The area of the semiconductor chip accounts for only a small percent of the mounting area.
If the ratio of a formation area of the semiconductor chip to the mounting area is designated as a "factor of effective area", it can be shown that this factor of effective area is extremely small in a semiconductor device molded by resin. If the factor of effective area is small, when the semiconductor device 20 which is connected with other circuit elements installed on the wiring substrate 30 is used, most of the mounting area will be dead space, which is not relevant to the chip's functions. The dead space on the mounting substrate will also be large as described above, thereby limiting density miniaturization of the mounting substrate 30.
This problem is especially remarkable in a semiconductor device of small package size. For example, if the package of a semiconductor chip is as shown in FIG. 3, the minimum size 3.4 mm .times.2.4 mm, and the semiconductor chip is wired with metal lead terminals and then molded by resin, the overall size of the semiconductor device will be approximately 6.0 mm.times.5.0 mm. The area of the chip of the semiconductor device will be 8.16 mm.sup.2, and the mounting area of the semiconductor will be 30.0 mm.sup.2. Thus, the factor of effective area of the semiconductor device will be approximately 27.2 percent, even though leads are ignored (when leads are taken into consideration, the value will be smaller.). Most of the mounting area will be a dead space.
In common consumer electronic devices such as, for example a portable digital assistants, 8 mm video cameras, portable telephones, cameras, and liquid crystal televisions, miniaturization of the body of such equipment requires the miniaturization of the mounting substrate.
However, in the resin sealing type semiconductor device described above, the dead space accounts for a large percent of the mounting area of the semiconductor device. This limits the miniaturization of mounting substrate, and results in this dead space being one of the factors preventing electronic devices from being miniaturized.
Japanese Patent Laid-Open Publication No. Hei 3-248551 discloses one method of improving the factor of effective area, as is shown in FIG. 4. In this method, in order to reduce the mounting area as much as possible when a resin mold type semiconductor device is mounted on a mounting substrate or the like, lead terminals 41, 42, and 43 are formed in such a manner that these terminals do not protrude from any side faces of a resin mold 44 and are on the same surface with the side faces of the resin mold 40. These lead terminals are connected with a base, an emitter, and a collector electrode of a semiconductor device 40.
With such constitution, the mounting area can be reduced by a portion of the tips of the lead terminals 41, 42, and 43 which retract into the side faces of the resin mold 44, and the factor of effective area can be slightly improved. However, the resulting improvement to the size of the dead space is not great.
To improve the factor of effective area, the area of a semiconductor chip in a semiconductor device should be almost the same as the mounting area. In the resin mold type semiconductor device, even though the tips of lead terminals do not protrude from the side faces of the resin mold like the prior art, it is difficult to improve the factor of effective area due to the presence of the mold resin.
Further, in the semiconductor device described above, since lead terminals connected to the semiconductor chip and mold resin are both indispensable, processes of wire connection of the semiconductor chip and the lead terminals and of injection molding of resin can not be dispensed with, meaning that the manufacturing process can not be simplified and that manufacturing costs can not be reduced.
In order to maximize the factor of effective area, as described above, it must be possible to make the area of the semiconductor chip almost equal to the mounting area by mounting the semiconductor chip directly on the mounting substrate.
Known method of mounting a semiconductor chip on a substrate, such as a mounting substrate, is shown in FIG. 5, which illustrates a technology of face down bonding of a flip chip on which a plurality of bump electrodes 46 are formed on a semiconductor chip 45 as disclosed in Japanese Patent Laid-Open Publication No. Hei 6-338504. However, in a semiconductor device joined by such face down bonding, problems, such as the peeling of bump electrodes from the semiconductor device, often arise when stress, such as thermal stress, is applied to the bump electrodes.
Another known art for mounting a semiconductor chip on a substrate such as a mounting substrate is the technology of die bonding a semiconductor chip 53 on a conductive pattern 52, which is formed on a mounting substrate 51, and connecting an electrode of the conductive pattern 52 arranged around the semiconductor chip 53 and its electrode by means of a wire 54, as is disclosed in Japanese Patent Laid-Open Publication No. Hei 7-38334 (see FIG. 6).
A fine line of gold is normally used as a wire for connecting the semiconductor chip 53 and the conductive pattern 52 which is arranged around the semiconductor chip 53. It is preferable to carry out bonding in a heated atmosphere of approximately 200 degrees centigrade to 300 degrees centigrade in order to increase peel strength (pull strength) at a section of bonding junction which is connected with the fine gold line by bonding.
However, when die bonding of the semiconductor chip on the mounting substrate of insulating resin system is performed, if heating temperature is raised to a temperature as described above, the wiring substrate will be warped. In order to melt solder used for fixing other circuit elements, such as a chip condenser and chip resistor, which are mounted on the mounting substrate, wire bonding junction is attained by setting the heating temperature to approximately 100 degrees centigrade to 150 degrees centigrade. However, there is then a problem that peel strength at a section of bonding junction is lowered.
In this method, a semiconductor chip is coated by thermohardening resin, such as epoxy resin after undergoing die bonding. As described above, however, low temperature wire bonding leads to decreased bond strength, whereby the joint of a bonding section peels due to a shrinkage of the epoxy resin at the time of heat curing.